Arlet's FPGA page


These are some hobby projects I've made with a Xilinx Spartan-3 starter kit.

VGA demo

Three rotating planes of colored squares. See movie clip.
Verilog source files: main.v, vga.v

Improved VGA timing generator

I've improved the VGA code to be smaller and faster. The goal is to increase the pixel clock using the built-in DCM module, and increase the resolution. The vga.v module only generates the timing signals for a standard 640x480 VGA screen. It is used in the VGA serializer module that generates a bitstream, see vga_serial.v.

VGA sprites

Using 640x480 TFT module, I made several versions of a sprite engine, with increasing capabilities. Animations can be found here:

Real-time proportional text rendering

Using Spartan-6 and CS4954 PAL/NTSC video generator, I made a rendering engine for proportional text. The text is stored in a block RAM, and displayed real-time on the screen. Here is a picture I took from the TV set showing the result:

This engine uses 4 block RAMs. One to hold the (max 2048) bytes of text, one for the font metrics, one to keep pointers to the bitmaps, and the last one to store all the bitmaps. Both interlaced and non-interlaced (at half the vertical resolution) are supported. Unlike traditional character generators (like the one below), the RAM does not hold the characters in a fixed grid. Instead, the characters are stored as a normal text string. If there's a CR in the string, the "cursor" moves back to the beginning of the line, and if there's a LF, it moves to the next line. This means that if you insert a CRLF sequence in the middle of the string, all the text following it will now be placed on the lines below.

6502 clone

A verilog model of the old 6502 CPU.

Character generator

Character generator using block RAM. Screen shot with camera
Screen shot 2, with text memory. Get the ROM contents as INIT_xx attributes.

Clock domain handshake module

A simple bidirectional handshake module which produces enable signals for two parallel data paths crossing clock domains in two directions. Some speed has been sacrificed for simplicity. I use it to pass FIFO head/tail pointers across clock domains.

E-mail. I also do freelance work (verilog, hardware, embedded software, linux), so if you need something different, let me know.